OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Rev 90

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4015d 21h /mod_sim_exp/trunk/sim/Makefile
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4087d 06h /mod_sim_exp/trunk/sim/Makefile
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4129d 01h /mod_sim_exp/trunk/sim/Makefile
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4136d 20h /mod_sim_exp/trunk/sim/Makefile
41 removed deprecated files from version control JonasDC 4234d 03h /mod_sim_exp/trunk/sim/Makefile
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4248d 06h /mod_sim_exp/trunk/sim/Makefile
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4248d 06h /mod_sim_exp/trunk/sim/Makefile
28 updated makefile for new pipeline sources JonasDC 4248d 20h /mod_sim_exp/trunk/sim/Makefile
24 changed names of top-level module to mod_sim_exp_core JonasDC 4252d 05h /mod_sim_exp/trunk/sim/Makefile
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4263d 21h /mod_sim_exp/trunk/sim/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.