URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk] - Rev 37

Rev	Log message	Author	Age	Path
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4227d 22h	/mod_sim_exp/trunk
16	package with modified generic parameter for register_n	JonasDC	4228d 11h	/mod_sim_exp/trunk
15	changed generic for register width from n to width for consistency	JonasDC	4228d 11h	/mod_sim_exp/trunk
14	changed comments, file is now according to OC design rules	JonasDC	4228d 11h	/mod_sim_exp/trunk
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4228d 11h	/mod_sim_exp/trunk
12	updated comments, file is now completely according to design rules	JonasDC	4228d 11h	/mod_sim_exp/trunk
11	simulation output folder	JonasDC	4228d 14h	/mod_sim_exp/trunk
10	changed signal input port names to correct name	JonasDC	4228d 16h	/mod_sim_exp/trunk
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4228d 16h	/mod_sim_exp/trunk
8	added descriptive comments	JonasDC	4228d 19h	/mod_sim_exp/trunk