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[/] [mod_sim_exp/] [trunk] - Rev 47

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Rev Log message Author Age Path
47 added documentation for the IP core. JonasDC 4172d 02h /mod_sim_exp/trunk
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4172d 03h /mod_sim_exp/trunk
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4172d 03h /mod_sim_exp/trunk
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4175d 20h /mod_sim_exp/trunk
43 made the core parameters generics JonasDC 4175d 20h /mod_sim_exp/trunk
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4182d 04h /mod_sim_exp/trunk
41 removed deprecated files from version control JonasDC 4182d 04h /mod_sim_exp/trunk
40 adjusted core instantiation to new core module name JonasDC 4190d 08h /mod_sim_exp/trunk
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4190d 19h /mod_sim_exp/trunk
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4191d 01h /mod_sim_exp/trunk
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4194d 22h /mod_sim_exp/trunk
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4195d 18h /mod_sim_exp/trunk
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4195d 20h /mod_sim_exp/trunk
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4195d 22h /mod_sim_exp/trunk
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4196d 00h /mod_sim_exp/trunk
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4196d 01h /mod_sim_exp/trunk
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4196d 06h /mod_sim_exp/trunk
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4196d 07h /mod_sim_exp/trunk
29 added software for generation of test input for the tesbenches JonasDC 4196d 20h /mod_sim_exp/trunk
28 updated makefile for new pipeline sources JonasDC 4196d 21h /mod_sim_exp/trunk

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