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[/] [mod_sim_exp/] [trunk] - Rev 92

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Rev	Log message	Author	Age	Path
92	updated documentation with minor interrupt changes of AXI interface	JonasDC	3952d 19h	/mod_sim_exp/trunk
91	changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register.	JonasDC	3954d 22h	/mod_sim_exp/trunk
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3956d 13h	/mod_sim_exp/trunk
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4020d 11h	/mod_sim_exp/trunk
88	small update on documentation, changed fault in axi control_reg	JonasDC	4026d 12h	/mod_sim_exp/trunk
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4026d 13h	/mod_sim_exp/trunk
86	update on previous	JonasDC	4026d 13h	/mod_sim_exp/trunk
85	changed so that reset now also affects slave register	JonasDC	4026d 13h	/mod_sim_exp/trunk
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4027d 21h	/mod_sim_exp/trunk
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4029d 22h	/mod_sim_exp/trunk
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4046d 18h	/mod_sim_exp/trunk
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4046d 18h	/mod_sim_exp/trunk
78	updated documentation with new RAM style information	JonasDC	4056d 12h	/mod_sim_exp/trunk
77	found fault in code, now synthesizes normally	JonasDC	4062d 10h	/mod_sim_exp/trunk
76	testbench update	JonasDC	4064d 21h	/mod_sim_exp/trunk
75	made rw_address a vector of a fixed width	JonasDC	4064d 21h	/mod_sim_exp/trunk
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4067d 17h	/mod_sim_exp/trunk
73	updated plb interface, mem_style and device generics added	JonasDC	4068d 16h	/mod_sim_exp/trunk
72	deleted old resources	JonasDC	4069d 16h	/mod_sim_exp/trunk
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4069d 16h	/mod_sim_exp/trunk

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[/] [mod_sim_exp/] [trunk] - Rev 92

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