URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk] - Rev 92

Rev	Log message	Author	Age	Path
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4082d 03h	/mod_sim_exp/trunk
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4082d 03h	/mod_sim_exp/trunk
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4082d 06h	/mod_sim_exp/trunk
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4082d 06h	/mod_sim_exp/trunk
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4089d 22h	/mod_sim_exp/trunk
64	added synthesis reports of xilinx and altera	JonasDC	4090d 04h	/mod_sim_exp/trunk
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4090d 04h	/mod_sim_exp/trunk
62	not used anymore	JonasDC	4090d 06h	/mod_sim_exp/trunk
61	updated comments, added optional altera constraint	JonasDC	4090d 06h	/mod_sim_exp/trunk
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4092d 21h	/mod_sim_exp/trunk