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[/] [mod_sim_exp] - Rev 104

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Rev Log message Author Age Path
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4028d 13h /mod_sim_exp
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4030d 14h /mod_sim_exp
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4047d 10h /mod_sim_exp
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4047d 10h /mod_sim_exp
80 renamed to version 1.1 to follow the versioning system JonasDC 4057d 04h /mod_sim_exp
79 Tag for version 1.3 (with new ram style JonasDC 4057d 04h /mod_sim_exp
78 updated documentation with new RAM style information JonasDC 4057d 04h /mod_sim_exp
77 found fault in code, now synthesizes normally JonasDC 4063d 01h /mod_sim_exp
76 testbench update JonasDC 4065d 12h /mod_sim_exp
75 made rw_address a vector of a fixed width JonasDC 4065d 12h /mod_sim_exp

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