URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp] - Rev 24

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4199d 05h	/mod_sim_exp
23	added descriptive comments	JonasDC	4199d 06h	/mod_sim_exp
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4202d 00h	/mod_sim_exp
21	changed x_i signal to xi	JonasDC	4203d 07h	/mod_sim_exp
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4203d 08h	/mod_sim_exp
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4208d 03h	/mod_sim_exp
18	updated stages with comments and renamed some signals for consistency	JonasDC	4209d 02h	/mod_sim_exp
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4209d 07h	/mod_sim_exp
16	package with modified generic parameter for register_n	JonasDC	4209d 20h	/mod_sim_exp
15	changed generic for register width from n to width for consistency	JonasDC	4209d 21h	/mod_sim_exp
14	changed comments, file is now according to OC design rules	JonasDC	4209d 21h	/mod_sim_exp
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4209d 21h	/mod_sim_exp
12	updated comments, file is now completely according to design rules	JonasDC	4209d 21h	/mod_sim_exp
11	simulation output folder	JonasDC	4209d 23h	/mod_sim_exp
10	changed signal input port names to correct name	JonasDC	4210d 02h	/mod_sim_exp
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4210d 02h	/mod_sim_exp
8	added descriptive comments	JonasDC	4210d 04h	/mod_sim_exp
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4210d 05h	/mod_sim_exp
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4210d 05h	/mod_sim_exp
5	not needed on svn, is generated by testbench	JonasDC	4210d 05h	/mod_sim_exp

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp] - Rev 24

Filtering Options