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[/] [mod_sim_exp] - Rev 30

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30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4195d 21h /mod_sim_exp
29 added software for generation of test input for the tesbenches JonasDC 4196d 11h /mod_sim_exp
28 updated makefile for new pipeline sources JonasDC 4196d 11h /mod_sim_exp
27 test input values for multiplier_tb JonasDC 4196d 11h /mod_sim_exp
26 testbench for only the montgommery multiplier JonasDC 4196d 11h /mod_sim_exp
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4196d 11h /mod_sim_exp
24 changed names of top-level module to mod_sim_exp_core JonasDC 4199d 20h /mod_sim_exp
23 added descriptive comments JonasDC 4199d 21h /mod_sim_exp
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4202d 15h /mod_sim_exp
21 changed x_i signal to xi JonasDC 4203d 23h /mod_sim_exp
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4203d 23h /mod_sim_exp
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4208d 18h /mod_sim_exp
18 updated stages with comments and renamed some signals for consistency JonasDC 4209d 17h /mod_sim_exp
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4209d 22h /mod_sim_exp
16 package with modified generic parameter for register_n JonasDC 4210d 12h /mod_sim_exp
15 changed generic for register width from n to width for consistency JonasDC 4210d 12h /mod_sim_exp
14 changed comments, file is now according to OC design rules JonasDC 4210d 12h /mod_sim_exp
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4210d 12h /mod_sim_exp
12 updated comments, file is now completely according to design rules JonasDC 4210d 12h /mod_sim_exp
11 simulation output folder JonasDC 4210d 15h /mod_sim_exp

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