OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp] - Rev 54

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4099d 19h /mod_sim_exp
53 correctly inferred ram for altera dual port ram JonasDC 4100d 01h /mod_sim_exp
52 correct inferring of blockram, no additional resources. JonasDC 4100d 02h /mod_sim_exp
51 true dual port ram for xilinx JonasDC 4100d 02h /mod_sim_exp
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4100d 02h /mod_sim_exp
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.		 JonasDC 4111d 21h /mod_sim_exp
48 Tag of the starting version of the project JonasDC 4111d 22h /mod_sim_exp
47 added documentation for the IP core. JonasDC 4180d 02h /mod_sim_exp
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4180d 02h /mod_sim_exp
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4180d 02h /mod_sim_exp
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4183d 20h /mod_sim_exp
43 made the core parameters generics JonasDC 4183d 20h /mod_sim_exp
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4190d 04h /mod_sim_exp
41 removed deprecated files from version control JonasDC 4190d 04h /mod_sim_exp
40 adjusted core instantiation to new core module name JonasDC 4198d 08h /mod_sim_exp
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4198d 19h /mod_sim_exp
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4199d 01h /mod_sim_exp
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4202d 21h /mod_sim_exp
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4203d 18h /mod_sim_exp
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4203d 20h /mod_sim_exp

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.