URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp] - Rev 8

Rev	Log message	Author	Age	Path
8	added descriptive comments	JonasDC	4213d 03h	/mod_sim_exp
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4213d 03h	/mod_sim_exp
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4213d 04h	/mod_sim_exp
5	not needed on svn, is generated by testbench	JonasDC	4213d 04h	/mod_sim_exp
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4213d 05h	/mod_sim_exp
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4213d 19h	/mod_sim_exp
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4218d 01h	/mod_sim_exp
1	The project and the structure was created	root	4220d 01h	/mod_sim_exp