URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 13

Rev	Log message	Author	Age	Path
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4214d 09h	/
12	updated comments, file is now completely according to design rules	JonasDC	4214d 09h	/
11	simulation output folder	JonasDC	4214d 11h	/
10	changed signal input port names to correct name	JonasDC	4214d 14h	/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4214d 14h	/
8	added descriptive comments	JonasDC	4214d 16h	/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4214d 16h	/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4214d 16h	/
5	not needed on svn, is generated by testbench	JonasDC	4214d 17h	/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4214d 18h	/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4215d 08h	/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4219d 14h	/
1	The project and the structure was created	root	4221d 14h	/