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Rev Log message Author Age Path
18 updated stages with comments and renamed some signals for consistency JonasDC 4188d 03h /
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4188d 08h /
16 package with modified generic parameter for register_n JonasDC 4188d 21h /
15 changed generic for register width from n to width for consistency JonasDC 4188d 21h /
14 changed comments, file is now according to OC design rules JonasDC 4188d 21h /
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4188d 22h /
12 updated comments, file is now completely according to design rules JonasDC 4188d 22h /
11 simulation output folder JonasDC 4189d 00h /
10 changed signal input port names to correct name JonasDC 4189d 03h /
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4189d 03h /
8 added descriptive comments JonasDC 4189d 05h /
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4189d 05h /
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4189d 06h /
5 not needed on svn, is generated by testbench JonasDC 4189d 06h /
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4189d 07h /
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4189d 21h /
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4194d 03h /
1 The project and the structure was created root 4196d 03h /

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