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Rev Log message Author Age Path
40 adjusted core instantiation to new core module name JonasDC 4190d 16h /
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4191d 03h /
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4191d 08h /
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4195d 05h /
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4196d 02h /
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4196d 04h /
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4196d 05h /
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4196d 08h /
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4196d 09h /
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4196d 14h /
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4196d 15h /
29 added software for generation of test input for the tesbenches JonasDC 4197d 04h /
28 updated makefile for new pipeline sources JonasDC 4197d 04h /
27 test input values for multiplier_tb JonasDC 4197d 04h /
26 testbench for only the montgommery multiplier JonasDC 4197d 04h /
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4197d 05h /
24 changed names of top-level module to mod_sim_exp_core JonasDC 4200d 13h /
23 added descriptive comments JonasDC 4200d 15h /
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4203d 08h /
21 changed x_i signal to xi JonasDC 4204d 16h /

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