| Rev |
Log message |
Author |
Age |
Path |
| 51 |
true dual port ram for xilinx |
JonasDC |
4109d 03h |
/ |
| 50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4109d 03h |
/ |
| 49 |
First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives. |
JonasDC |
4120d 22h |
/ |
| 48 |
Tag of the starting version of the project |
JonasDC |
4120d 22h |
/ |
| 47 |
added documentation for the IP core. |
JonasDC |
4189d 02h |
/ |
| 46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4189d 03h |
/ |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4189d 03h |
/ |
| 44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4192d 20h |
/ |
| 43 |
made the core parameters generics |
JonasDC |
4192d 20h |
/ |
| 42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4199d 04h |
/ |
| 41 |
removed deprecated files from version control |
JonasDC |
4199d 04h |
/ |
| 40 |
adjusted core instantiation to new core module name |
JonasDC |
4207d 08h |
/ |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4207d 19h |
/ |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4208d 01h |
/ |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4211d 22h |
/ |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4212d 18h |
/ |
| 35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4212d 20h |
/ |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4212d 22h |
/ |
| 33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4213d 00h |
/ |
| 32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4213d 01h |
/ |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4213d 07h |
/ |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4213d 07h |
/ |
| 29 |
added software for generation of test input for the tesbenches |
JonasDC |
4213d 20h |
/ |
| 28 |
updated makefile for new pipeline sources |
JonasDC |
4213d 21h |
/ |
| 27 |
test input values for multiplier_tb |
JonasDC |
4213d 21h |
/ |
| 26 |
testbench for only the montgommery multiplier |
JonasDC |
4213d 21h |
/ |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4213d 21h |
/ |
| 24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4217d 06h |
/ |
| 23 |
added descriptive comments |
JonasDC |
4217d 07h |
/ |
| 22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4220d 01h |
/ |
