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Rev	Log message	Author	Age	Path
56	this is a branch to test performance of a new style of ram	JonasDC	4082d 21h	/
55	updated resource usage in comments	JonasDC	4083d 18h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4083d 18h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4084d 01h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4084d 01h	/
51	true dual port ram for xilinx	JonasDC	4084d 02h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4084d 02h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4095d 21h	/
48	Tag of the starting version of the project	JonasDC	4095d 21h	/
47	added documentation for the IP core.	JonasDC	4164d 02h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4164d 02h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4164d 02h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4167d 19h	/
43	made the core parameters generics	JonasDC	4167d 19h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4174d 03h	/
41	removed deprecated files from version control	JonasDC	4174d 03h	/
40	adjusted core instantiation to new core module name	JonasDC	4182d 07h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4182d 18h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4183d 00h	/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4186d 21h	/

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[/] - Rev 56

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