Rev |
Log message |
Author |
Age |
Path |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4087d 19h |
/ |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4087d 19h |
/ |
58 |
made fifo full a warning |
JonasDC |
4090d 19h |
/ |
57 |
new fifo design, is now generic (verified with altera and xilinx) and uses block ram |
JonasDC |
4090d 19h |
/ |
56 |
this is a branch to test performance of a new style of ram |
JonasDC |
4090d 22h |
/ |
55 |
updated resource usage in comments |
JonasDC |
4091d 19h |
/ |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4091d 19h |
/ |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4092d 01h |
/ |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4092d 02h |
/ |
51 |
true dual port ram for xilinx |
JonasDC |
4092d 02h |
/ |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4092d 03h |
/ |
49 |
First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives. |
JonasDC |
4103d 22h |
/ |
48 |
Tag of the starting version of the project |
JonasDC |
4103d 22h |
/ |
47 |
added documentation for the IP core. |
JonasDC |
4172d 02h |
/ |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4172d 02h |
/ |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4172d 02h |
/ |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4175d 20h |
/ |
43 |
made the core parameters generics |
JonasDC |
4175d 20h |
/ |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4182d 04h |
/ |
41 |
removed deprecated files from version control |
JonasDC |
4182d 04h |
/ |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4190d 08h |
/ |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4190d 19h |
/ |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4191d 01h |
/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4194d 22h |
/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4195d 18h |
/ |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4195d 20h |
/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4195d 21h |
/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4196d 00h |
/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4196d 01h |
/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4196d 06h |
/ |