URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 60

Rev	Log message	Author	Age	Path
40	adjusted core instantiation to new core module name	JonasDC	4189d 21h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4190d 09h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4190d 14h	/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4194d 11h	/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4195d 07h	/
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4195d 10h	/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4195d 11h	/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4195d 14h	/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4195d 15h	/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4195d 20h	/