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Subversion Repositories mod_sim_exp

[/] - Rev 67

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Rev	Log message	Author	Age	Path
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4078d 00h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4078d 00h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4085d 16h	/
64	added synthesis reports of xilinx and altera	JonasDC	4085d 21h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4085d 21h	/
62	not used anymore	JonasDC	4086d 00h	/
61	updated comments, added optional altera constraint	JonasDC	4086d 00h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4088d 14h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4088d 15h	/
58	made fifo full a warning	JonasDC	4091d 15h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4091d 15h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4091d 18h	/
55	updated resource usage in comments	JonasDC	4092d 14h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4092d 15h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4092d 21h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4092d 22h	/
51	true dual port ram for xilinx	JonasDC	4092d 22h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4092d 22h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4104d 17h	/
48	Tag of the starting version of the project	JonasDC	4104d 18h	/
47	added documentation for the IP core.	JonasDC	4172d 22h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4172d 22h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4172d 22h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4176d 16h	/
43	made the core parameters generics	JonasDC	4176d 16h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4183d 00h	/
41	removed deprecated files from version control	JonasDC	4183d 00h	/
40	adjusted core instantiation to new core module name	JonasDC	4191d 04h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4191d 15h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4191d 20h	/

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Subversion Repositories mod_sim_exp

[/] - Rev 67

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