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Rev Log message Author Age Path
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4101d 18h /
68 branch no longer needed JonasDC 4101d 20h /
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4101d 21h /
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4101d 21h /
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4109d 13h /
64 added synthesis reports of xilinx and altera JonasDC 4109d 18h /
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4109d 18h /
62 not used anymore JonasDC 4109d 21h /
61 updated comments, added optional altera constraint JonasDC 4109d 21h /
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4112d 11h /
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4112d 12h /
58 made fifo full a warning JonasDC 4115d 12h /
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 4115d 12h /
56 this is a branch to test performance of a new style of ram JonasDC 4115d 15h /
55 updated resource usage in comments JonasDC 4116d 11h /
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4116d 11h /
53 correctly inferred ram for altera dual port ram JonasDC 4116d 18h /
52 correct inferring of blockram, no additional resources. JonasDC 4116d 18h /
51 true dual port ram for xilinx JonasDC 4116d 19h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 4116d 19h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4128d 14h /
48 Tag of the starting version of the project JonasDC 4128d 14h /
47 added documentation for the IP core. JonasDC 4196d 19h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4196d 19h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4196d 19h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4200d 13h /
43 made the core parameters generics JonasDC 4200d 13h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4206d 20h /
41 removed deprecated files from version control JonasDC 4206d 20h /
40 adjusted core instantiation to new core module name JonasDC 4215d 01h /

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