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Rev	Log message	Author	Age	Path
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4102d 02h	/
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4166d 00h	/
88	small update on documentation, changed fault in axi control_reg	JonasDC	4172d 01h	/
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4172d 02h	/
86	update on previous	JonasDC	4172d 02h	/
85	changed so that reset now also affects slave register	JonasDC	4172d 02h	/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4173d 10h	/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4175d 11h	/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4192d 07h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4192d 07h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4202d 01h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4202d 01h	/
78	updated documentation with new RAM style information	JonasDC	4202d 01h	/
77	found fault in code, now synthesizes normally	JonasDC	4207d 23h	/
76	testbench update	JonasDC	4210d 10h	/
75	made rw_address a vector of a fixed width	JonasDC	4210d 10h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4213d 06h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4214d 05h	/
72	deleted old resources	JonasDC	4215d 05h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4215d 05h	/

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[/] - Rev 90

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