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Subversion Repositories mod_sim_exp

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Rev	Log message	Author	Age	Path
92	updated documentation with minor interrupt changes of AXI interface	JonasDC	3963d 01h	/
91	changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register.	JonasDC	3965d 04h	/
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3966d 19h	/
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4030d 17h	/
88	small update on documentation, changed fault in axi control_reg	JonasDC	4036d 18h	/
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4036d 19h	/
86	update on previous	JonasDC	4036d 19h	/
85	changed so that reset now also affects slave register	JonasDC	4036d 19h	/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4038d 03h	/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4040d 04h	/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4057d 00h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4057d 00h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4066d 18h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4066d 18h	/
78	updated documentation with new RAM style information	JonasDC	4066d 18h	/
77	found fault in code, now synthesizes normally	JonasDC	4072d 16h	/
76	testbench update	JonasDC	4075d 03h	/
75	made rw_address a vector of a fixed width	JonasDC	4075d 03h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4077d 23h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4078d 22h	/
72	deleted old resources	JonasDC	4079d 22h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4079d 22h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4079d 22h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4079d 22h	/
68	branch no longer needed	JonasDC	4080d 00h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4080d 01h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4080d 01h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4087d 17h	/
64	added synthesis reports of xilinx and altera	JonasDC	4087d 23h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4087d 23h	/

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