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Rev Log message Author Age Path
79 Tag for version 1.3 (with new ram style JonasDC 3603d 16h /
78 updated documentation with new RAM style information JonasDC 3603d 16h /
77 found fault in code, now synthesizes normally JonasDC 3609d 13h /
76 testbench update JonasDC 3612d 00h /
75 made rw_address a vector of a fixed width JonasDC 3612d 00h /
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 3614d 20h /
73 updated plb interface, mem_style and device generics added JonasDC 3615d 19h /
72 deleted old resources JonasDC 3616d 20h /
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 3616d 20h /
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3616d 20h /

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