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[/] [neorv32/] [trunk/] [sw/] [lib/] [include/] - Rev 18

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Rev Log message Author Age Path
18 updated to version 1.3.6.0
see NEORV32.pdf for more information		 zero_gravity 1396d 16h /neorv32/trunk/sw/lib/include/
16 minor edits; buck fixes in PMP
see changelog in NEORV32.pdf for more information		 zero_gravity 1400d 19h /neorv32/trunk/sw/lib/include/
15 updated to HW version 1.3.5.0
see changelog in NEORV32.pdf for more information		 zero_gravity 1401d 19h /neorv32/trunk/sw/lib/include/
14 update to HW version 1.3.0.0
see changelog in NEORV32.pdf for more information		 zero_gravity 1406d 00h /neorv32/trunk/sw/lib/include/
13 updates, optimizations and bug fixes; see changelog in NEORV32.pdf zero_gravity 1409d 16h /neorv32/trunk/sw/lib/include/
12 Processor version 1.2.0.5 - see changelog in NEORV32.pdf zero_gravity 1410d 23h /neorv32/trunk/sw/lib/include/
11 new hardware version, see changelog in NEORV32.pdf zero_gravity 1420d 18h /neorv32/trunk/sw/lib/include/
10 minor updates and front page modifications zero_gravity 1423d 16h /neorv32/trunk/sw/lib/include/
9 minor edits and updates zero_gravity 1423d 18h /neorv32/trunk/sw/lib/include/
8 added missing FENCE instruction; added optional Zifencei CPU extension zero_gravity 1424d 16h /neorv32/trunk/sw/lib/include/
7 removed "mtinst" CSR since it is not ratified yet by the RISC-V specs zero_gravity 1424d 19h /neorv32/trunk/sw/lib/include/
6 new processor version: 1.0.0.0 -> increased performance; debugged errors; processor now passes risc-v compliance tests; see changelog for more information zero_gravity 1425d 15h /neorv32/trunk/sw/lib/include/
4 see NEORV32.pdf for changelog zero_gravity 1434d 00h /neorv32/trunk/sw/lib/include/
3 general updates, see changelog in NEORV32.pdf for more information zero_gravity 1435d 18h /neorv32/trunk/sw/lib/include/
2 - initial commit zero_gravity 1436d 19h /neorv32/trunk/sw/lib/include/

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