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[/] [open8_urisc/] - Rev 206

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Rev Log message Author Age Path
206 Merged interrupt logic with other clocked process. jshamlet 1511d 17h /open8_urisc/
205 More code and comment cleanup for the new SDLC engine jshamlet 1511d 17h /open8_urisc/
204 Fixed more incorrect comments jshamlet 1511d 18h /open8_urisc/
203 Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. jshamlet 1512d 00h /open8_urisc/
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.		 jshamlet 1512d 01h /open8_urisc/
201 Fixed comments regarding RX Checksum location jshamlet 1513d 22h /open8_urisc/
200 Renamed dual-port buffer to match other entities. jshamlet 1513d 22h /open8_urisc/
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1513d 22h /open8_urisc/
198 Removed debugging memory jshamlet 1514d 06h /open8_urisc/
197 Fixed incorrect comments jshamlet 1514d 07h /open8_urisc/
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1514d 07h /open8_urisc/
195 Added dual-port RAM core for SDLC interface. jshamlet 1515d 02h /open8_urisc/
194 Cleaned up licensing sections jshamlet 1515d 02h /open8_urisc/
193 Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. jshamlet 1515d 03h /open8_urisc/
192 Added SDLC packet engine jshamlet 1515d 03h /open8_urisc/
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1515d 03h /open8_urisc/
190 Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00.		 jshamlet 1527d 00h /open8_urisc/
189 Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals.		 jshamlet 1528d 01h /open8_urisc/
188 Added a generic to alter the behavior of RTI so that it can optionally skip restoring the general purpose flags GP4 to GP7, allowing ISR's to make persistent changes to them. Also exported these flags to the top level for use outside the CPU. jshamlet 1528d 04h /open8_urisc/
187 Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. jshamlet 1530d 00h /open8_urisc/

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