URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 305

Rev	Log message	Author	Age	Path
285	Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments.	jshamlet	1139d 23h	/open8_urisc/
284	Corrected the vhdl unit name and description for o8_7seg.vhd	jshamlet	1253d 10h	/open8_urisc/
283	Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop.	jshamlet	1256d 22h	/open8_urisc/
282	Modified the SDLC core transmit states to have consistent naming.	jshamlet	1256d 22h	/open8_urisc/
281	Added pre-initialization to the dual-port RAM signals.	jshamlet	1257d 01h	/open8_urisc/
280	Got rid of silly aliases that connected the dual-port memory and the arbitration logic.	jshamlet	1257d 02h	/open8_urisc/
279	More comment cleanup	jshamlet	1257d 23h	/open8_urisc/
278	Flattened the SDLC interface to fewer files and eliminated the package file.	jshamlet	1258d 17h	/open8_urisc/
277	Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag.	jshamlet	1258d 23h	/open8_urisc/
276	More comment fixes	jshamlet	1293d 19h	/open8_urisc/