OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] - Rev 234

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
234 Forgot to add documentation jshamlet 1491d 19h /open8_urisc/trunk/
233 Updated the Sample Projects.zip jshamlet 1491d 19h /open8_urisc/trunk/
232 More code cleanup on sample projects. SDLC2LCD should now match the Open8_II project model. jshamlet 1500d 22h /open8_urisc/trunk/
231 Updated sample projects and added elapsed time capture (chronometer) module jshamlet 1500d 23h /open8_urisc/trunk/
230 Added two sample projects that show how to connect and program an Open8 system jshamlet 1504d 09h /open8_urisc/trunk/
229 Created a new version of the system timer with 24-bit, 1-uS resolution. The new timer has a much different register interface, so it is now o8_sys_timer_ii. jshamlet 1504d 20h /open8_urisc/trunk/
228 Added an initialization constant for the OPEN8_BUS_TYPE record. jshamlet 1505d 10h /open8_urisc/trunk/
227 Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. jshamlet 1505d 17h /open8_urisc/trunk/
226 Forgot the updated package file... jshamlet 1505d 20h /open8_urisc/trunk/
225 Added Halt_Ack to go with Halt_Req. jshamlet 1505d 20h /open8_urisc/trunk/
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1505d 22h /open8_urisc/trunk/
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1506d 16h /open8_urisc/trunk/
222 Created a modified version of the epoch timer with a 32-bit, 1-uS resolution timer/comparator. jshamlet 1506d 21h /open8_urisc/trunk/
221 o8_vdsm8.vhd now has a default value assigned at compile time, o8_register.vhd was cleaned up some more. jshamlet 1507d 16h /open8_urisc/trunk/
220 More revision sections added jshamlet 1507d 16h /open8_urisc/trunk/
219 Added revision block and corrected creation date. jshamlet 1507d 16h /open8_urisc/trunk/
218 Revision sections added,
vdsm8.vhd added.
jshamlet 1507d 16h /open8_urisc/trunk/
217 Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup.
jshamlet 1507d 16h /open8_urisc/trunk/
216 Fixed missing parenthesis jshamlet 1507d 18h /open8_urisc/trunk/
215 More code cleanup jshamlet 1507d 19h /open8_urisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.