OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [Documents/] [CPU Instruction Set_files/] [sheet002.htm] - Rev 311

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
311 Updated documentation to reflect generic switch controlling ROR/ROL behavior and the carry bit jshamlet 397d 09h /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm
277 Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag. jshamlet 1243d 10h /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm
272 Updated the HTML documentation to reflect the removed generic. jshamlet 1290d 09h /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm
241 Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation. jshamlet 1458d 05h /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.