URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 312

Rev	Log message	Author	Age	Path
282	Modified the SDLC core transmit states to have consistent naming.	jshamlet	1264d 20h	/open8_urisc/trunk/VHDL/
281	Added pre-initialization to the dual-port RAM signals.	jshamlet	1264d 23h	/open8_urisc/trunk/VHDL/
280	Got rid of silly aliases that connected the dual-port memory and the arbitration logic.	jshamlet	1265d 00h	/open8_urisc/trunk/VHDL/
279	More comment cleanup	jshamlet	1265d 21h	/open8_urisc/trunk/VHDL/
278	Flattened the SDLC interface to fewer files and eliminated the package file.	jshamlet	1266d 15h	/open8_urisc/trunk/VHDL/
276	More comment fixes	jshamlet	1301d 17h	/open8_urisc/trunk/VHDL/
275	Fixed a minor comment error.	jshamlet	1303d 11h	/open8_urisc/trunk/VHDL/
274	Updated comments with more corrections	jshamlet	1303d 18h	/open8_urisc/trunk/VHDL/
273	Updated comments with corrections	jshamlet	1303d 20h	/open8_urisc/trunk/VHDL/
271	Removed deleted generic define.	jshamlet	1313d 19h	/open8_urisc/trunk/VHDL/