URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 314

Rev	Log message	Author	Age	Path
284	Corrected the vhdl unit name and description for o8_7seg.vhd	jshamlet	1251d 12h	/open8_urisc/trunk/VHDL/
283	Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop.	jshamlet	1254d 23h	/open8_urisc/trunk/VHDL/
282	Modified the SDLC core transmit states to have consistent naming.	jshamlet	1255d 00h	/open8_urisc/trunk/VHDL/
281	Added pre-initialization to the dual-port RAM signals.	jshamlet	1255d 02h	/open8_urisc/trunk/VHDL/
280	Got rid of silly aliases that connected the dual-port memory and the arbitration logic.	jshamlet	1255d 03h	/open8_urisc/trunk/VHDL/
279	More comment cleanup	jshamlet	1256d 00h	/open8_urisc/trunk/VHDL/
278	Flattened the SDLC interface to fewer files and eliminated the package file.	jshamlet	1256d 18h	/open8_urisc/trunk/VHDL/
276	More comment fixes	jshamlet	1291d 21h	/open8_urisc/trunk/VHDL/
275	Fixed a minor comment error.	jshamlet	1293d 15h	/open8_urisc/trunk/VHDL/
274	Updated comments with more corrections	jshamlet	1293d 22h	/open8_urisc/trunk/VHDL/