URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 317

Rev	Log message	Author	Age	Path
287	Fixed mangled comments and revisioning dates.	jshamlet	1120d 09h	/open8_urisc/trunk/VHDL/
286	Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands.	jshamlet	1120d 09h	/open8_urisc/trunk/VHDL/
285	Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments.	jshamlet	1127d 12h	/open8_urisc/trunk/VHDL/
284	Corrected the vhdl unit name and description for o8_7seg.vhd	jshamlet	1240d 23h	/open8_urisc/trunk/VHDL/
283	Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop.	jshamlet	1244d 11h	/open8_urisc/trunk/VHDL/
282	Modified the SDLC core transmit states to have consistent naming.	jshamlet	1244d 11h	/open8_urisc/trunk/VHDL/
281	Added pre-initialization to the dual-port RAM signals.	jshamlet	1244d 14h	/open8_urisc/trunk/VHDL/
280	Got rid of silly aliases that connected the dual-port memory and the arbitration logic.	jshamlet	1244d 15h	/open8_urisc/trunk/VHDL/
279	More comment cleanup	jshamlet	1245d 12h	/open8_urisc/trunk/VHDL/
278	Flattened the SDLC interface to fewer files and eliminated the package file.	jshamlet	1246d 06h	/open8_urisc/trunk/VHDL/