OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 325

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
325 Added the rest of the initializers to the signal assignments jshamlet 247d 07h /open8_urisc/trunk/VHDL/
324 Modified the Open8 version of the multi-channel roll average code to have separate interrupt enables for average and flush operations. Note that the flush status bit should be checked by software prior to use if the Autoflush_On_Reset generic is set TRUE.

Also adding the ROMTAPE entity, which acts as a serial-access ROM for storing strings, arrays, etc. in order to alleviate pressure on the primary program ROM. It is intended for use with loops that load fixed content from ROM.		 jshamlet 247d 07h /open8_urisc/trunk/VHDL/
323 Forgot to add files jshamlet 248d 06h /open8_urisc/trunk/VHDL/
322 Performance fixes for the LCD interface,
Fixed incorrect entity name for the dual LTC2355 IF,
Added a CPU-accessible 8-channel averager core and FIFO-style ROM		 jshamlet 248d 06h /open8_urisc/trunk/VHDL/
321 Fixed issue with parity flag in receiver sticking jshamlet 351d 23h /open8_urisc/trunk/VHDL/
320 Inverted flow control signals to match EIA-232 specification jshamlet 354d 02h /open8_urisc/trunk/VHDL/
319 Fixed off-by-one error in channel count jshamlet 355d 05h /open8_urisc/trunk/VHDL/
318 Added o8_scale_conv.vhd and intdiv.vhd jshamlet 359d 07h /open8_urisc/trunk/VHDL/
317 Altered the reinit signal on teh adc128s022.vhd driver to be optional, and removed the "dead" signal from the upper level o8_de0_nano_adc_if.vhd code. jshamlet 373d 04h /open8_urisc/trunk/VHDL/
316 More code cleanup and comments,
Removed INT_VECTOR_n constants, as they are superfluous. There are no reasonable situations in which the constants would be altered.		 jshamlet 373d 04h /open8_urisc/trunk/VHDL/
315 Added Terasic DE0 Nano ADC interface and rolling averager. jshamlet 373d 05h /open8_urisc/trunk/VHDL/
314 Code cleanup and added comments jshamlet 373d 06h /open8_urisc/trunk/VHDL/
313 Added all generics to package component jshamlet 373d 07h /open8_urisc/trunk/VHDL/
312 Added o8_timer24.vhd as a more flexible alternative to o8_sys_timer_ii.vhd.
Also cleaned up some comments in the HTML documentation		 jshamlet 373d 07h /open8_urisc/trunk/VHDL/
310 Added optional DACadv signal to advance the PWM engine using an external signal. This is used to synchronize the DAC with other DACs or for streaming multiple streams across a high-speed serial link. jshamlet 444d 09h /open8_urisc/trunk/VHDL/
308 jshamlet 465d 23h /open8_urisc/trunk/VHDL/
307 Fixed comments on o8_version.vhd jshamlet 673d 09h /open8_urisc/trunk/VHDL/
299 Modified the status_led.vhd to slow down the DIM50PCT signal to 1/32 instead of 1/2 for use with shift-register based discrete LEDs and added the ability to chain the toggle signal to save on resources as well as synchronize the "toggling" jshamlet 681d 21h /open8_urisc/trunk/VHDL/
298 Fixed a long-standing bug in the SBC instruction where the 1 wasn't being added to complete the 2's complement of Rn. This was causing off-by-one errors in subtraction and negating carry only subtractions. jshamlet 682d 23h /open8_urisc/trunk/VHDL/
297 Fixed register map comments jshamlet 973d 07h /open8_urisc/trunk/VHDL/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.