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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_async_serial.vhd] - Rev 320

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Rev Log message Author Age Path
320 Inverted flow control signals to match EIA-232 specification jshamlet 515d 09h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
293 Fixed formatting issue in o8_sync_serial where tabs were inserted instead of spaces and fixed column spacing as a result (purely cosmetic) jshamlet 1165d 14h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
274 Updated comments with more corrections jshamlet 1461d 10h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
244 Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.

Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.

Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.

Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock.
jshamlet 1627d 09h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1661d 16h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1662d 09h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
217 Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup.
jshamlet 1663d 09h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
213 Code and comment cleanup jshamlet 1667d 10h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.
jshamlet 1669d 05h /open8_urisc/trunk/VHDL/o8_async_serial.vhd
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1670d 08h /open8_urisc/trunk/VHDL/o8_async_serial.vhd

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