OpenCores

URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 291

Go to most recent revision

Filtering Options

Rev	Log message	Author	Age	Path
271	Removed deleted generic define.	jshamlet	1294d 20h	/
270	Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally. Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.	jshamlet	1294d 20h	/
269	Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance.	jshamlet	1297d 09h	/
268	Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL.	jshamlet	1297d 10h	/
267	Corrected the file description to indicate this is an example package.	jshamlet	1297d 10h	/
266	Accidentally uploaded incorrect example file for Open8_cfg.vhd	jshamlet	1297d 10h	/
265	Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset.	jshamlet	1389d 19h	/
264	Updated comments	jshamlet	1399d 16h	/
263	Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES. Also separated the SDLC TX and RX interrupts so that they could be handled separately.	jshamlet	1399d 16h	/
262	Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map.	jshamlet	1408d 20h	/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.