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[/] [openarty/] - Rev 43

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Rev Log message Author Age Path
43 Cleaned up the CPU memory documentation. dgisselq 2746d 06h /openarty/
42 Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test.		 dgisselq 2746d 06h /openarty/
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2746d 06h /openarty/
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2746d 06h /openarty/
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2746d 06h /openarty/
38 ZipLoad can now load programs to non-reset locations. dgisselq 2746d 06h /openarty/
37 Updated documentation and copyright. dgisselq 2746d 06h /openarty/
36 Lots of changes, see the git changelog for details. dgisselq 2752d 15h /openarty/
35 Added comments and copyright notice. dgisselq 2756d 03h /openarty/
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2756d 05h /openarty/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2761d 11h /openarty/
32 Brought the CPU to its first working version, to include demo. dgisselq 2762d 14h /openarty/
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2763d 06h /openarty/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2763d 06h /openarty/
29 Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator.		 dgisselq 2791d 03h /openarty/
28 Including the updates and corrections from the wbuart32 project. dgisselq 2791d 03h /openarty/
27 Bus changes ... dgisselq 2791d 03h /openarty/
26 Adjusted the timing comments. dgisselq 2791d 03h /openarty/
25 The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v.		 dgisselq 2799d 11h /openarty/
24 Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board.		 dgisselq 2818d 07h /openarty/

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