URL https://opencores.org/ocsvn/openarty/openarty/trunk

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[/] [openarty/] [trunk/] - Rev 43

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Rev	Log message	Author	Age	Path
43	Cleaned up the CPU memory documentation.	dgisselq	2745d 15h	/openarty/trunk/
42	Fixed up the CPU so that it passes a multiply test bench, in addition to the CPU test.	dgisselq	2745d 15h	/openarty/trunk/
41	Added the CPU test program to the Arty distribution. This works.	dgisselq	2745d 15h	/openarty/trunk/
40	Fixed a problem with the declaration of variables to be volatile.	dgisselq	2745d 15h	/openarty/trunk/
39	Fixes the OLED test so that it runs using the DMA.	dgisselq	2745d 15h	/openarty/trunk/
38	ZipLoad can now load programs to non-reset locations.	dgisselq	2745d 15h	/openarty/trunk/
37	Updated documentation and copyright.	dgisselq	2745d 15h	/openarty/trunk/
36	Lots of changes, see the git changelog for details.	dgisselq	2752d 00h	/openarty/trunk/
35	Added comments and copyright notice.	dgisselq	2755d 11h	/openarty/trunk/
34	These updates bring the distribution along to the point where both the GPS clock subsecond tracking, as well as the OLEDrgb controller now work.	dgisselq	2755d 13h	/openarty/trunk/
33	Fixed the network receive CRC and MAC checking, and added ip-checking and minimum packet length checking to the receiver.	dgisselq	2760d 20h	/openarty/trunk/
32	Brought the CPU to its first working version, to include demo.	dgisselq	2761d 22h	/openarty/trunk/
31	Initial network is now working. Adding CPU control files to repository.	dgisselq	2762d 15h	/openarty/trunk/
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2762d 15h	/openarty/trunk/
29	Here's the memory pin list, necessary for running Xilinx's Memory Interface Generator.	dgisselq	2790d 12h	/openarty/trunk/
28	Including the updates and corrections from the wbuart32 project.	dgisselq	2790d 12h	/openarty/trunk/
27	Bus changes ...	dgisselq	2790d 12h	/openarty/trunk/
26	Adjusted the timing comments.	dgisselq	2790d 12h	/openarty/trunk/
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	2798d 20h	/openarty/trunk/
24	Here are the updates from the first (failed) attempt to try to integrate the DDR3 SDRAM controller onto this board.	dgisselq	2817d 16h	/openarty/trunk/

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Subversion Repositories openarty

[/] [openarty/] [trunk/] - Rev 43

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