| Rev |
Log message |
Author |
Age |
Path |
| 43 |
Cleaned up the CPU memory documentation. |
dgisselq |
2745d 11h |
/openarty/trunk/rtl/ |
| 42 |
Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test. |
dgisselq |
2745d 11h |
/openarty/trunk/rtl/ |
| 36 |
Lots of changes, see the git changelog for details. |
dgisselq |
2751d 20h |
/openarty/trunk/rtl/ |
| 34 |
These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work. |
dgisselq |
2755d 09h |
/openarty/trunk/rtl/ |
| 33 |
Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver. |
dgisselq |
2760d 15h |
/openarty/trunk/rtl/ |
| 32 |
Brought the CPU to its first working version, to include demo. |
dgisselq |
2761d 18h |
/openarty/trunk/rtl/ |
| 31 |
Initial network is now working. Adding CPU control files to repository. |
dgisselq |
2762d 11h |
/openarty/trunk/rtl/ |
| 30 |
Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz. |
dgisselq |
2762d 11h |
/openarty/trunk/rtl/ |
| 27 |
Bus changes ... |
dgisselq |
2790d 08h |
/openarty/trunk/rtl/ |
| 26 |
Adjusted the timing comments. |
dgisselq |
2790d 08h |
/openarty/trunk/rtl/ |
| 25 |
The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v. |
dgisselq |
2798d 16h |
/openarty/trunk/rtl/ |
| 24 |
Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board. |
dgisselq |
2817d 12h |
/openarty/trunk/rtl/ |
| 21 |
Removed the OLED controller one additional clock from the bus. This was
necessary to maintain the 200MHz clock speed, especially given the growing
fanout of the device bus. |
dgisselq |
2827d 11h |
/openarty/trunk/rtl/ |
| 20 |
Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before. |
dgisselq |
2827d 11h |
/openarty/trunk/rtl/ |
| 19 |
Creates an LED mask portion of writing to the LED's register. Only those
bits specified in the mask (bits [7:4]) will be adjusted in the LED
register on a write. Hence to set all on, set the LED register to 0x0ff,
all off, 0x0f0, or to set LED 0 to on while leaving the others unchanged,
set it to 0x011. |
dgisselq |
2827d 11h |
/openarty/trunk/rtl/ |
| 17 |
Fixed the misaddressed I/O peripherals in the fastio peripheral group. In
particular, UART and GPS were misaddressed. This has now been fixed, so these
peripherals (should) match the spec. Further, the default speed of the two
UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the
GPS UART. The Aux UART transmitter also passes testing, so at least that one
works. |
dgisselq |
2829d 10h |
/openarty/trunk/rtl/ |
| 13 |
Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v). |
dgisselq |
2829d 12h |
/openarty/trunk/rtl/ |
| 12 |
A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build. |
dgisselq |
2830d 15h |
/openarty/trunk/rtl/ |
| 3 |
Initial set of files. The flash appears to work, memory hasn't been started,
the MDIO controller works in simulation, etc. Everything below fasttop.v works
at 200MHz (not the CPU---yet). |
dgisselq |
2845d 18h |
/openarty/trunk/rtl/ |
