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[/] [openarty/] [trunk/] [rtl/] [busmaster.v] - Rev 49

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Rev	Log message	Author	Age	Path
49	Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants more friendly and more complete, fixed two bugs in the CPU (jumps to breaks, and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more. Rebuild any user programs before using this build.	dgisselq	2725d 08h	/openarty/trunk/rtl/busmaster.v
36	Lots of changes, see the git changelog for details.	dgisselq	2751d 21h	/openarty/trunk/rtl/busmaster.v
34	These updates bring the distribution along to the point where both the GPS clock subsecond tracking, as well as the OLEDrgb controller now work.	dgisselq	2755d 10h	/openarty/trunk/rtl/busmaster.v
33	Fixed the network receive CRC and MAC checking, and added ip-checking and minimum packet length checking to the receiver.	dgisselq	2760d 16h	/openarty/trunk/rtl/busmaster.v
32	Brought the CPU to its first working version, to include demo.	dgisselq	2761d 19h	/openarty/trunk/rtl/busmaster.v
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2762d 12h	/openarty/trunk/rtl/busmaster.v
27	Bus changes ...	dgisselq	2790d 09h	/openarty/trunk/rtl/busmaster.v
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	2798d 17h	/openarty/trunk/rtl/busmaster.v
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	2845d 19h	/openarty/trunk/rtl/busmaster.v

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