URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [cpu/] [busdelay.v] - Rev 32

Rev	Log message	Author	Age	Path
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2760d 23h	/openarty/trunk/rtl/cpu/busdelay.v
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	2844d 07h	/openarty/trunk/rtl/cpu/busdelay.v