URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [fastmaster.v] - Rev 24

Rev	Log message	Author	Age	Path
24	Here are the updates from the first (failed) attempt to try to integrate the DDR3 SDRAM controller onto this board.	dgisselq	2810d 13h	/openarty/trunk/rtl/fastmaster.v
17	Fixed the misaddressed I/O peripherals in the fastio peripheral group. In particular, UART and GPS were misaddressed. This has now been fixed, so these peripherals (should) match the spec. Further, the default speed of the two UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the GPS UART. The Aux UART transmitter also passes testing, so at least that one works.	dgisselq	2822d 12h	/openarty/trunk/rtl/fastmaster.v
13	Here are the updates necessary to get the initial Quad SPI flash driver working. This includes in particular the bus interconnect (in fastmaster.v), and the final hookup to the external wires (in fasttop.v).	dgisselq	2822d 13h	/openarty/trunk/rtl/fastmaster.v
12	A work in progress. This checkin contains fixes for the flash (mostly), together with some logic reductions facilitating full speed (200MHz) build.	dgisselq	2823d 16h	/openarty/trunk/rtl/fastmaster.v
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	2838d 20h	/openarty/trunk/rtl/fastmaster.v