URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [wbddrsdram.v] - Rev 24

Rev	Log message	Author	Age	Path
24	Here are the updates from the first (failed) attempt to try to integrate the DDR3 SDRAM controller onto this board.	dgisselq	2802d 22h	/openarty/trunk/rtl/wbddrsdram.v
17	Fixed the misaddressed I/O peripherals in the fastio peripheral group. In particular, UART and GPS were misaddressed. This has now been fixed, so these peripherals (should) match the spec. Further, the default speed of the two UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the GPS UART. The Aux UART transmitter also passes testing, so at least that one works.	dgisselq	2814d 21h	/openarty/trunk/rtl/wbddrsdram.v
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	2831d 05h	/openarty/trunk/rtl/wbddrsdram.v