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[/] [openarty/] [trunk/] [sw/] - Rev 36

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36 Lots of changes, see the git changelog for details. dgisselq 2753d 06h /openarty/trunk/sw/
35 Added comments and copyright notice. dgisselq 2756d 17h /openarty/trunk/sw/
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2756d 19h /openarty/trunk/sw/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2762d 01h /openarty/trunk/sw/
32 Brought the CPU to its first working version, to include demo. dgisselq 2763d 04h /openarty/trunk/sw/
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2763d 21h /openarty/trunk/sw/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2763d 21h /openarty/trunk/sw/
22 A useful script for programming the device, given that the current device
program includes a valid comms interface.		 dgisselq 2828d 21h /openarty/trunk/sw/
18 The device can now program and configure itself, allowing bootstrap possibilities.
`		 dgisselq 2828d 21h /openarty/trunk/sw/
16 This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects.		 dgisselq 2830d 21h /openarty/trunk/sw/
14 All changes made as a part of getting the flash driver up and running. Today,
it successfully programmed a configuration into the Arty via wbprogram, so ...
that's been my last/best test.		 dgisselq 2830d 22h /openarty/trunk/sw/
6 Minor updates, mostly to support the development of the DDR3 SDRAM--such
as creating addresses for the debugging scope used to figure out what's
going on with it.		 dgisselq 2832d 01h /openarty/trunk/sw/
4 Initial host software pack. dgisselq 2847d 04h /openarty/trunk/sw/

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