OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [sw/] - Rev 59

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Removed no-longer-used files. dgisselq 2597d 04h /openarty/trunk/sw/
54 Added in a working C-library for the ZipCPU.

Provides stdin/stdout support.		 dgisselq 2597d 04h /openarty/trunk/sw/
53 Removing the artyboard.h file from the dev directory. dgisselq 2597d 04h /openarty/trunk/sw/
52 Updated sw for the Arty. dgisselq 2597d 04h /openarty/trunk/sw/
51 Updated host software, following 8-bit byte updates. dgisselq 2597d 04h /openarty/trunk/sw/
49 Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants
more friendly and more complete, fixed two bugs in the CPU (jumps to breaks,
and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more.
Rebuild any user programs before using this build.		 dgisselq 2721d 17h /openarty/trunk/sw/
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2741d 22h /openarty/trunk/sw/
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2741d 22h /openarty/trunk/sw/
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2741d 22h /openarty/trunk/sw/
38 ZipLoad can now load programs to non-reset locations. dgisselq 2741d 22h /openarty/trunk/sw/
37 Updated documentation and copyright. dgisselq 2741d 22h /openarty/trunk/sw/
36 Lots of changes, see the git changelog for details. dgisselq 2748d 07h /openarty/trunk/sw/
35 Added comments and copyright notice. dgisselq 2751d 18h /openarty/trunk/sw/
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2751d 20h /openarty/trunk/sw/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2757d 02h /openarty/trunk/sw/
32 Brought the CPU to its first working version, to include demo. dgisselq 2758d 05h /openarty/trunk/sw/
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2758d 22h /openarty/trunk/sw/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2758d 22h /openarty/trunk/sw/
22 A useful script for programming the device, given that the current device
program includes a valid comms interface.		 dgisselq 2823d 22h /openarty/trunk/sw/
18 The device can now program and configure itself, allowing bootstrap possibilities.
`		 dgisselq 2823d 22h /openarty/trunk/sw/
16 This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects.		 dgisselq 2825d 22h /openarty/trunk/sw/
14 All changes made as a part of getting the flash driver up and running. Today,
it successfully programmed a configuration into the Arty via wbprogram, so ...
that's been my last/best test.		 dgisselq 2825d 23h /openarty/trunk/sw/
6 Minor updates, mostly to support the development of the DDR3 SDRAM--such
as creating addresses for the debugging scope used to figure out what's
going on with it.		 dgisselq 2827d 02h /openarty/trunk/sw/
4 Initial host software pack. dgisselq 2842d 05h /openarty/trunk/sw/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.