URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [sw/] [host/] [Makefile] - Rev 30

Rev	Log message	Author	Age	Path
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2762d 23h	/openarty/trunk/sw/host/Makefile
18	The device can now program and configure itself, allowing bootstrap possibilities. `	dgisselq	2827d 23h	/openarty/trunk/sw/host/Makefile
14	All changes made as a part of getting the flash driver up and running. Today, it successfully programmed a configuration into the Arty via wbprogram, so ... that's been my last/best test.	dgisselq	2830d 00h	/openarty/trunk/sw/host/Makefile
6	Minor updates, mostly to support the development of the DDR3 SDRAM--such as creating addresses for the debugging scope used to figure out what's going on with it.	dgisselq	2831d 03h	/openarty/trunk/sw/host/Makefile
4	Initial host software pack.	dgisselq	2846d 06h	/openarty/trunk/sw/host/Makefile