URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] - Rev 12

Rev	Log message	Author	Age	Path
12	A work in progress. This checkin contains fixes for the flash (mostly), together with some logic reductions facilitating full speed (200MHz) build.	dgisselq	2823d 16h	/
11	Files necessary to simulate the entire Arty board--everything at the fastmaster module and below.	dgisselq	2823d 16h	/
10	Updated flash data and test files, for a flash that produces it's answers a clock after I'm expecting them.	dgisselq	2823d 16h	/
9	Adding copywrite statement (oops).	dgisselq	2823d 16h	/
8	Fixes the makefile so it builds a complete testbench suite, emulating the entire Arty board.	dgisselq	2823d 16h	/
7	This implements the coordination of a massive build/test suite--just not the actual configuration file itself.	dgisselq	2823d 16h	/
6	Minor updates, mostly to support the development of the DDR3 SDRAM--such as creating addresses for the debugging scope used to figure out what's going on with it.	dgisselq	2823d 16h	/
5	Initial checkin, this time of the bench testing s/w.	dgisselq	2838d 19h	/
4	Initial host software pack.	dgisselq	2838d 19h	/
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	2838d 19h	/
2	Initial documentation/proposed specification. (I'm writing the spec as I'm building the core.)	dgisselq	2839d 14h	/
1	The project and the structure was created	root	2839d 17h	/