| Rev |
Log message |
Author |
Age |
Path |
| 25 |
The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v. |
dgisselq |
2789d 00h |
/ |
| 24 |
Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board. |
dgisselq |
2807d 19h |
/ |
| 23 |
Includes settings necessary for the Arty to load from flash builds, and to
reconfigure itself later. |
dgisselq |
2817d 18h |
/ |
| 22 |
A useful script for programming the device, given that the current device
program includes a valid comms interface. |
dgisselq |
2817d 18h |
/ |
| 21 |
Removed the OLED controller one additional clock from the bus. This was
necessary to maintain the 200MHz clock speed, especially given the growing
fanout of the device bus. |
dgisselq |
2817d 19h |
/ |
| 20 |
Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before. |
dgisselq |
2817d 19h |
/ |
| 19 |
Creates an LED mask portion of writing to the LED's register. Only those
bits specified in the mask (bits [7:4]) will be adjusted in the LED
register on a write. Hence to set all on, set the LED register to 0x0ff,
all off, 0x0f0, or to set LED 0 to on while leaving the others unchanged,
set it to 0x011. |
dgisselq |
2817d 19h |
/ |
| 18 |
The device can now program and configure itself, allowing bootstrap possibilities.
` |
dgisselq |
2817d 19h |
/ |
| 17 |
Fixed the misaddressed I/O peripherals in the fastio peripheral group. In
particular, UART and GPS were misaddressed. This has now been fixed, so these
peripherals (should) match the spec. Further, the default speed of the two
UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the
GPS UART. The Aux UART transmitter also passes testing, so at least that one
works. |
dgisselq |
2819d 18h |
/ |
| 16 |
This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects. |
dgisselq |
2819d 18h |
/ |
| 15 |
These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed. |
dgisselq |
2819d 19h |
/ |
| 14 |
All changes made as a part of getting the flash driver up and running. Today,
it successfully programmed a configuration into the Arty via wbprogram, so ...
that's been my last/best test. |
dgisselq |
2819d 19h |
/ |
| 13 |
Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v). |
dgisselq |
2819d 19h |
/ |
| 12 |
A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build. |
dgisselq |
2820d 22h |
/ |
| 11 |
Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below. |
dgisselq |
2820d 22h |
/ |
| 10 |
Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them. |
dgisselq |
2820d 22h |
/ |
| 9 |
Adding copywrite statement (oops). |
dgisselq |
2820d 22h |
/ |
| 8 |
Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board. |
dgisselq |
2820d 22h |
/ |
| 7 |
This implements the coordination of a massive build/test suite--just not the
actual configuration file itself. |
dgisselq |
2820d 22h |
/ |
| 6 |
Minor updates, mostly to support the development of the DDR3 SDRAM--such
as creating addresses for the debugging scope used to figure out what's
going on with it. |
dgisselq |
2820d 22h |
/ |
