URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] - Rev 34

Rev	Log message	Author	Age	Path
14	All changes made as a part of getting the flash driver up and running. Today, it successfully programmed a configuration into the Arty via wbprogram, so ... that's been my last/best test.	dgisselq	2828d 18h	/
13	Here are the updates necessary to get the initial Quad SPI flash driver working. This includes in particular the bus interconnect (in fastmaster.v), and the final hookup to the external wires (in fasttop.v).	dgisselq	2828d 19h	/
12	A work in progress. This checkin contains fixes for the flash (mostly), together with some logic reductions facilitating full speed (200MHz) build.	dgisselq	2829d 21h	/
11	Files necessary to simulate the entire Arty board--everything at the fastmaster module and below.	dgisselq	2829d 21h	/
10	Updated flash data and test files, for a flash that produces it's answers a clock after I'm expecting them.	dgisselq	2829d 21h	/
9	Adding copywrite statement (oops).	dgisselq	2829d 21h	/
8	Fixes the makefile so it builds a complete testbench suite, emulating the entire Arty board.	dgisselq	2829d 21h	/
7	This implements the coordination of a massive build/test suite--just not the actual configuration file itself.	dgisselq	2829d 21h	/
6	Minor updates, mostly to support the development of the DDR3 SDRAM--such as creating addresses for the debugging scope used to figure out what's going on with it.	dgisselq	2829d 21h	/
5	Initial checkin, this time of the bench testing s/w.	dgisselq	2845d 01h	/