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Rev Log message Author Age Path
44 Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time.		 dgisselq 2737d 18h /
43 Cleaned up the CPU memory documentation. dgisselq 2737d 18h /
42 Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test.		 dgisselq 2737d 18h /
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2737d 18h /
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2737d 18h /
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2737d 18h /
38 ZipLoad can now load programs to non-reset locations. dgisselq 2737d 18h /
37 Updated documentation and copyright. dgisselq 2737d 18h /
36 Lots of changes, see the git changelog for details. dgisselq 2744d 04h /
35 Added comments and copyright notice. dgisselq 2747d 15h /
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2747d 17h /
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2752d 23h /
32 Brought the CPU to its first working version, to include demo. dgisselq 2754d 02h /
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2754d 18h /
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2754d 18h /
29 Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator.		 dgisselq 2782d 15h /
28 Including the updates and corrections from the wbuart32 project. dgisselq 2782d 15h /
27 Bus changes ... dgisselq 2782d 15h /
26 Adjusted the timing comments. dgisselq 2782d 16h /
25 The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v.		 dgisselq 2791d 00h /

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