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Rev Log message Author Age Path
50 Updated the CPU and distribution in general to handle 8-bit bytes. dgisselq 2595d 23h /
49 Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants
more friendly and more complete, fixed two bugs in the CPU (jumps to breaks,
and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more.
Rebuild any user programs before using this build.		 dgisselq 2720d 12h /
48 Greatly expanded the specification, including how to's, getting started guide,
register definitions, etc.		 dgisselq 2723d 01h /
47 Updated. dgisselq 2740d 16h /
46 Sped the UART simulator back up to 1MBaud. dgisselq 2740d 16h /
45 Updated the flash, and the flash test bench, for Quad I/O read commands. dgisselq 2740d 16h /
44 Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time.		 dgisselq 2740d 16h /
43 Cleaned up the CPU memory documentation. dgisselq 2740d 16h /
42 Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test.		 dgisselq 2740d 16h /
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2740d 16h /
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2740d 16h /
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2740d 16h /
38 ZipLoad can now load programs to non-reset locations. dgisselq 2740d 16h /
37 Updated documentation and copyright. dgisselq 2740d 16h /
36 Lots of changes, see the git changelog for details. dgisselq 2747d 02h /
35 Added comments and copyright notice. dgisselq 2750d 13h /
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2750d 15h /
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2755d 21h /
32 Brought the CPU to its first working version, to include demo. dgisselq 2757d 00h /
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2757d 17h /

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