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Rev Log message Author Age Path
223 Adjust register mapping of FRAME_SELECT olivier.girard 2750d 05h /openmsp430/
222 Update to latest openGFX430 version. Update 2BPP demo. olivier.girard 2751d 06h /openmsp430/
221 Move old Altera-DE1 project to the OBSOLETE directory.
Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.		 olivier.girard 2828d 06h /openmsp430/
220 Create OBSOLETE directory to store old FPGA projects olivier.girard 2828d 07h /openmsp430/
219 Update overview html file olivier.girard 2844d 06h /openmsp430/
218 Update Tools Changelog olivier.girard 2844d 06h /openmsp430/
217 Update openmsp430-gdb-proxy tool to fix Get Register procedure when using the TI GDB (thanks to Simon Fröhlich for this one). olivier.girard 2844d 07h /openmsp430/
216 Add new donate picture. olivier.girard 2844d 07h /openmsp430/
215 Update ChangeLog olivier.girard 2986d 07h /openmsp430/
214 Fix multiwindow environment issue & close window with 'X'. Thanks to Fabian Mauroner for this one olivier.girard 2986d 07h /openmsp430/
213 Update ChangeLogs olivier.girard 3102d 16h /openmsp430/
212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3102d 16h /openmsp430/
211 Add custom printf function to reduce program memory footprint (the TI/RH GCC version is huge). Note that this function was created by DJ Delorie ( http://www.delorie.com/ ) olivier.girard 3102d 17h /openmsp430/
210 Add support for both MSPGCC and TI/RH-GCC toolchains. Add detection of debug ports for OS-X. olivier.girard 3102d 18h /openmsp430/
209 Update ChangeLogs olivier.girard 3130d 07h /openmsp430/
208 Update tools to run with latest CPU core version. olivier.girard 3130d 07h /openmsp430/
207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3130d 07h /openmsp430/
206 Update ChangeLog olivier.girard 3227d 07h /openmsp430/
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3227d 07h /openmsp430/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3234d 07h /openmsp430/

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