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[/] [openmsp430/] [trunk/] [core/] - Rev 106

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Rev	Log message	Author	Age	Path
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4802d 04h	/openmsp430/trunk/core/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4817d 04h	/openmsp430/trunk/core/
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4822d 11h	/openmsp430/trunk/core/
102	Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH instructions are now working as expected: - indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 - indirect autoincrement: PUSH @R1+	olivier.girard	4823d 04h	/openmsp430/trunk/core/
101	Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source.	olivier.girard	4823d 05h	/openmsp430/trunk/core/
99	Small fix for CVER simulator support.	olivier.girard	4827d 05h	/openmsp430/trunk/core/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4827d 05h	/openmsp430/trunk/core/
95	Update some test patterns for the additional simulator supports.	olivier.girard	4831d 05h	/openmsp430/trunk/core/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4831d 05h	/openmsp430/trunk/core/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4835d 06h	/openmsp430/trunk/core/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4858d 03h	/openmsp430/trunk/core/
85	Diverse RTL cosmetic updates.	olivier.girard	4858d 04h	/openmsp430/trunk/core/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4863d 06h	/openmsp430/trunk/core/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4912d 12h	/openmsp430/trunk/core/
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4924d 06h	/openmsp430/trunk/core/
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4929d 05h	/openmsp430/trunk/core/
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5011d 06h	/openmsp430/trunk/core/
73	Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh". This will prevent compatibility problems in systems where bash isn't the default shell.	olivier.girard	5036d 06h	/openmsp430/trunk/core/
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5038d 07h	/openmsp430/trunk/core/
68	Update synthesis scripts with the hardware multiplier support.	olivier.girard	5185d 14h	/openmsp430/trunk/core/

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] - Rev 106

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